DAQ PCI-DSP01 Manuel d'utilisateur Page 7

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PCI-DSP01 Users Manual (Rev 1.0)
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7- http://www.daqsystem.com
[TMS320C6205 DSP-CHIP 주요 특징]
High-Performance Fixed-Point Digital Signal Processor (DSP) − TMS320C6205
5-ns Instruction Cycle Time
200-MHz Clock Rate
Eight 32-Bit Instructions/Cycle
1600 MIPS
VelociTIAdvanced-Very-Long-Instruction- Word (VLIW) TMS320C62xDSP Core
Eight Highly Independent Functional Units:
Six ALUs (32-/40-Bit)
Two 16-Bit Multipliers (32-Bit Result)
Load-Store Architecture With 32 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Instruction Set Features
Byte-Addressable (8-, 16-, 32-Bit Data)
8-Bit Overflow Protection
Saturation
Bit-Field Extract, Set, Clear
Bit-Counting
Normalization
1M-Bit On-Chip SRAM
512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
512K-Bit Dual-Access Internal Data (64K Bytes)
Organized as Two 32K-Byte Blocks for Improved Concurrency
32-Bit External Memory Interface (EMIF)
Glueless Interface to Synchronous Memories: SDRAM or SBSRAM
Glueless Interface to Asynchronous Memories: SRAM and EPROM
52M-Byte Addressable External Memory Space
Four-Channel Boot loading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
Flexible Phase-Locked-Loop (PLL) Clock Generator
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